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White Electronic Designs
WV3EG232M64EFSU-D4
ADVANCED*
512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA
FEATURES
Fast data transfer rate: PC-2100 and PC-2700 Clock speeds of 133 MHz and 166 MHz Two data transfers per clock cycle Supports ECC error detection and correction Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2 and 2.5 (clock) Programmable Burst Length (2, 4 or 8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect (SPD) with EEPROM Dual Rank Power supply: VCC = VCCQ = +2.5V 0.2V (133 and 166MHz) Gold edge contacts 200 pin, small-outline, SO-DIMM package * PCB height option: 31.75 mm (1.25")
NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice.
DESCRIPTION
The WV3EG232M64EFSU is a 2x32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of sixteen 32Mx8 4 banks DDR SDRAMs in FBGA packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
OPERATING FREQUENCIES
DDR333@CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266@CL=2 133MHz 2-2-2 DDR266@CL=2.5 133MHz 2.5-3-3
April 2005 Rev. 0
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PIN CONFIGURATION
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 51 VSS 101 A9 151 DQ42 1 VREF 2 VREF 52 VSS 102 A8 152 DQ46 53 DQ19 103 VSS 153 DQ43 3 VSS 4 VSS 54 DQ23 104 VSS 154 DQ47 5 DQ0 55 DQ24 105 A7 155 VCC 6 DQ4 56 DQ28 106 A6 156 VCC 7 DQ1 57 VCC 107 A5 157 VCC 8 DQ5 58 VCC 108 A4 158 *CK1# 9 VCC 59 DQ25 109 A3 159 VSS 10 VCC 60 DQ29 110 A2 160 *CK1 11 DQS0 61 DQS3 111 A1 161 VSS 12 DM0 62 DM3 112 A0 162 VSS 13 DQ2 63 VSS 113 VCC 163 DQ48 14 DQ6 64 VSS 114 VCC 164 DQ52 65 DQ26 115 A10/AP 165 DQ49 15 VSS 16 VSS 66 DQ30 116 BA1 166 DQ53 17 DQ3 67 DQ27 117 BA0 167 VCC 18 DQ7 68 DQ31 118 RAS# 168 VCC 19 DQ8 69 VCC 119 WE# 169 DQS6 20 DQ12 70 VCC 120 CAS# 170 DM6 21 VCC 71 NC 121 CS0# 171 DQ50 22 VCC 72 NC 122 CS1# 172 DQ54 23 DQ9 73 NC 123 NC 173 VSS 24 DQ13 74 NC 124 NC 174 VSS 25 DQS1 75 VSS 125 VSS 175 DQ51 26 DM1 76 VSS 126 VSS 176 DQ55 27 VSS 77 DNU 127 DQ32 177 DQ56 78 DNU 128 DQ36 178 DQ60 28 VSS 29 DQ10 79 NC 129 DQ33 179 VCC 30 DQ14 80 NC 130 DQ37 180 VCC 31 DQ11 81 VCC 131 VCC 181 DQ57 32 DQ15 82 VCC 132 VCC 182 DQ61 83 NC 133 DQS4 183 DQS7 33 VCC 34 VCC 84 NC 134 DM4 184 DM7 35 CK0 85 NC 135 DQ34 185 VSS 36 VCC 86 NC 136 DQ38 186 VSS 37 CK0# 87 VSS 137 VSS 187 DQ58 38 VSS 88 VSS 138 VSS 188 DQ62 39 VSS 89 CK2* 139 DQ35 189 DQ59 40 VSS 90 VSS 140 DQ39 190 DQ63 41 DQ16 91 CK2#* 141 DQ40 191 VCC 42 DQ20 92 VCC* 142 DQ44 192 VCC 43 DQ17 93 VCC 143 VCC 193 SDA 44 DQ21 94 VCC 144 VCC 194 SA0 45 VCC 95 CKE1 145 DQ41 195 SCL 46 VCC 96 CKE0 146 DQ45 196 SA1 47 DQS2 97 NC 147 DQS5 197 VCCSPD 48 DM2 98 NC 148 DM5 198 SA2 49 DQ18 99 A12 149 VSS 199 NC 50 DQ22 100 A11 150 VSS 200 NC
WV3EG232M64EFSU-D4
ADVANCED
PIN NAMES
Symbol A0-A12 BA0, BA1 DQ0-DQ63 CK0, CK0# CKE0-CKE1 CS0#-CS1# WE#, CAS#, RAS# DQS0-DQS7 DM0-DM7 VCC VCCQ VCCSPD VREF VSS SCL SA0-SA2 VCCID SDA NC DNU RESET# Description Address input Bank Address Input/Output: Data I/Os, Data bus Clock Input Clock Enable Input Chip Select Input Command Input Data Strobe Data Write Mask Supply: Power Supply: +2.5V 0.2V Power Supply for DQS Supply: Serial EEPROM Positive Power Supply Supply: SSTL_2 reference voltage Supply: Ground Serial Clock Presence Detect Address Input VCC Identification Flag Input/Output: Serial Presence-Detect Data No Connect Do Not Use Reset Enable
* These pins are not used in this module.
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WV3EG232M64EFSU-D4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1# CKE1 CS0# CKE0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 DM2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS S0# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
BA0, BA1 A0-A12 RAS# CAS# WE# VCCSPD VCC VREF VSS
BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs WE#: DDR SDRAMs SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs CK0 CK0#
SERIAL PD SCL WP SDA A0 A1 A2 SA0 SA1 SA2
PLL
DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM
NOTE: 1.All resistor values are 22 unless otherwise specified.
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WV3EG232M64EFSU-D4
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VCC supply relative to Vss Voltage on VCCQ supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VCC VCCQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 16 50 Unit V V V C W mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
TA = 0C to 70C Parameter Supply voltage(for device with a nominal VCC of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK# inputs Input Differential Voltage, CK and CK# inputs Input crossing point voltage, CK and CK# inputs Input leakage current Output leakage current Output High Current(Normal strengh driver); VOUT = VTT + 0.84V Output High Current(Normal strengh driver); VOUT = VTT - 0.84V Output High Current(Half strengh driver); VOUT = VTT + 0.45V Output High Current(Half strengh driver); VOUT = VTT - 0.45V Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL Min 2.3 2.3 VCCQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 VCCQ/2+50mV VREF+0.04 VCCQ+0.3 VREF-0.15 VCCQ+0.3 VCCQ+0.6 1.35 2 5 Unit v V V V V V V V V uA uA mA mA mA mA Note
1 2 4 4 3 5
Notes: 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must track variations in the dc level of the same.
CAPACITANCE
VCC = 2.5, VCCQ = 2.5V, TA = 25 C, f = 1MHz Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1,RAS#, CAS#, WE#) Input capacitance (CKE0,CKE1) Input capacitance ( CS0#, CS1#) Input capacitance ( CK0, CK0#) Input capacitance (DM0~DM7) Data & DQS input/output capacitance (DQ0~DQ63)
April 2005 Rev. 0
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1
4
Min 38 38 36 36 12 12
Max 47 47 44 40 14 14
Unit pF pF pF pF pF pF
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0C TA +70C; VCC, VCCQ = +2.5V 0.2V
WV3EG232M64EFSU-D4
ADVANCED
IDD SPECIFICATIONS AND CONDITIONS
MAX PARAMETER/CONDITION Operating current - One bank Active-Precharge; tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating current - One bank operation ; One bank open, BL=4, Reads -- Refer to the following page for detailed test condition Percharge power-down standby current; All banks idle; power-down mode; CKE VIL(max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM Precharge Floating standby current; CS# VIH(min);All banks idle; CKE VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ,DQS and DM Precharge Quiet standby current; CS# VIH(min); All banks idle; CKE VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with keeping VIH(min) or VIL(max); VIN = VREF for DQ ,DQS and DM Active power - down standby current ; one bank active; power-down mode; CKE VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM Active standby current; CS# VIH(min); CKE VIH(min); one bank active; active - precharge; tRC = tRAS(max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst; lOUT = 0mA Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh Self refresh current; CKE 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B Orerating current - Four bank operation ; Four bank interleaving with BL=4 -- Refer to the following page for detailed test condition SYMBOL IDD0 DDR333 @CL=2.5 1160 DDR266 @CL=2 1000 DDR266 @CL=2.5 1000 UNITS mA
IDD1 IDD2P IDD2F
1360 48 400
1200 48 320
1200 48 320
mA mA mA
IDD2Q
320
290
290
mA
IDD3P IDD3N
560 880
480 720
480 720
mA mA
IDD4R
1720
1480
1480
mA
IDD4W
1720
1440
1440
mA
IDD5 IDD6 IDD7A
1800 48 2680
1640 48 2360
1640 48 2360
mA mA mA
Note: IDD specification is based on Samsung components. Other DRAM Manufacturers specification may be different.
April 2005 Rev. 0
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VCC = 2.5V, VCCQ = 2.5V, 0c TA +70C Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition
WV3EG232M64EFSU-D4
ADVANCED
AC OPERATIONG TEST CONDITIONS
Value 0.5 * VCCQ 1.5 VREF +0.31/VREF -0.31 VREF VTT See Load Circuit Unit V V V V V
OUTPUT LOAD CIRCUIT)
VTT =0.5*VCCQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VCCQ
April 2005 Rev. 0
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WV3EG232M64EFSU-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
0C TA +70C; VCC = VCCQ = +2.5V 0.2V AC Operating Test Conditions Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK# Output data access time from CK/CK# Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK# Data-out low impedence time from CK/CK# Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5 Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR 335 Min 60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 - 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 Max Min 65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 - 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 262 Max Min 65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 - 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 265 Max Unit ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns V/ns V/ns V/ns Note
70K
120K
120K
12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25
12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25
12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25
5 5
5
2
1.1
1.1
1.1
6 6 6 6
+0.7 +0.7
+0.75 +0.75
+0.75 +0.75
6 7
4.5 1.5
4.5 1.5
4.5 1.5
AC Timing Parameters are based on Samsung components. Other DRAM Manufacturers parameters may be different.
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WV3EG232M64EFSU-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
0C TA 70C, VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time Symbol tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL 335 Min 12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP-tQHS tCLmin or tCHmin 0.4 18 (tWR/tCK) + (tRP/tCK) Max Min 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP-tQHS tCLmin or tCHmin 0.4 20 (tWR/tCK) + (tRP/tCK) 262 Max Min 15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP-tQHS tCLmin or tCHmin 0.4 20 (tWR/tCK) + (tRP/tCK) 265 Max Unit ns ns ns ns ns ns ns tCK us ns ns ns tCK tCK 3 Note
7 7
4 1 5
-- -- 0.55 0.6
-- -- 0.75 0.6
-- -- 0.75 0.6
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3
tIS (ps) 0 +50 +100
tIH (ps) 0 +50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3
tDS (ps) 0 +75 +150
tDH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate.
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WV3EG232M64EFSU-D4
ADVANCED
ORDERING INFORMATION FOR D4
Part Number WV3EG232M64EFSU335D4xG WV3EG232M64EFSU262D4xG WV3EG232M64EFSU265D4xG Speed 166MHz/333Mbps 133MHz/266Mbps 133MHz/266Mbps CAS Latency 2.5 2 2.5 tRCD 3 2 3 tRP 3 2 3 Height* 31.75 (1.25") MAX 31.75 (1.25") MAX 31.75 (1.25") MAX
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
200-PIN DDR2 SODIMM DIMENSIONS
67.60 (2.66) 63.60 (2.50) Full R 2X 3.80 (0.150) MAX
4.00 0.10 (0.16 0.039) 20.00 (0.79)
1 39 41 199
31.75 (1.25)
6.00 (0.24)
1.10 (0.043) 2.15 (0.086) 11.40 (0.456) 4.20 (0.17) 2.40 (0.096) 1.80 (0.07) 2.45 (0.098) 1.00 0.1 (0.04 0.0039) 0.60 (0.024) 0.45 0.03 (0.018 0.001) 0.25 (0.01) 2.55 Min (0.102 Min) 47.40 (1.896) 2- 1.80 (0.07)
4.00 0.10 (0.16 0.0039)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
April 2005 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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WV3EG232M64EFSU-D4
ADVANCED
PART NUMBERING GUIDE
WV 3 E G 232M 64 E F S U xxx D4 x G
WEDC MEMORY DDR GOLD DEPTH (Dual Rank) BUS WIDTH x8 FBGA 2.5V UNBUFFERED SPEED (MHz) PACKAGE 200 PIN COMPONENT VENDOR NAME (M = MICRON) (S = SAMSUNG) RoHS COMPLIANT
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Document Title
WV3EG232M64EFSU-D4
ADVANCED
512MB - 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA
Revision History Rev #
Rev 0
History
Created
Release Date
4-05
Status
Advanced
April 2005 Rev. 0
11
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